2022 Flash Memory Summit Announcements

Enterprise Tech 2022 Flash Memory Summit Announcements Tom Coughlin Contributor Opinions expressed by Forbes Contributors are their own. New! Follow this author to stay notified about their latest stories. Got it! Aug 13, 2022, 11:37am EDT | New! Click on the conversation bubble to join the conversation Got it! Share to Facebook Share to Twitter Share to Linkedin Poster at the 2022 Flash Memory Summit Tom Coughlin Photo Although the FMS is broadening to include all solid-state storage, not just flash memory, there were several product and technology announcements at the 2022 Flash Memory Summit.

Let’s look at announcements by Kioxia, Western Digital, YMTC, FADU, Solidigm (SK hynix), Samsung, NVIDIA and Neo Semiconductor. During Kioxia’s keynote talk the company talked about its software-defined flash API (software-enabled flash) for more effective data center flash implementation. They said that their Ethernet attached SSDs can be used for storage disaggregation and is certified for GPUDirect storage.

The company is also offering E1. S (XD6) and E3. S (CM7) SSD form factors.

The CM7 debuted at the FMS. Kioxia, as well as the company’s factory partner, Western Digital, discussed NAND scaling. As the slide image below shows, 3D NAND flash memory density depends upon more factors than the number of layers.

In particular it also involves lateral scaling, logical scaling and architectural scaling (in particular chip or die stacking). Kioxia on sources for flash memory density improvements Tom Coughlin Photograph Western Digital also talked about NAND flash moving into adjacent market niches—such as providing storage class memory that supplements DRAM. They also talked about the various ways to scale NAND flash and showed a roadmap going out to over 500 layers by 2032 but also implementing other density enhancements as shown below.

Regarding logical scaling with more bits per cell, WDC talked about 4. 5 bits per cell products ahead of going to a full 5 bits per cell for cold storage applications. MORE FOR YOU The 5 Biggest Technology Trends In 2022 ‘Enthusiastic Entrepreneurs’: Pre-IPO Statements On Profitability Prove To Be Larger Than Real Life The 7 Biggest Artificial Intelligence (AI) Trends In 2022 WDC roadmap to 500 layers and other density improvements Photo by Tom Coughlin Some other design innovations that WDC talked about include asynchronous independent plane read (aIPR) for improved random read performance.

One slide said that total NAND flash annual capacity production in 2021 was 765EB with over 2ZB projected for 2025. YMTC out of China showed a picture of their manufacturing facility in China during their keynote talk. YMTC is pioneering wafer bonding of a logic wafer to 3D NAND flash wafers as a way to achieve high density NAND flash.

The wafer bonding is through millions of metal vias and YMTC calls this Xtacking. YMTC says that this enables smaller die sizes and higher bit densities. The company says that it has validated this wafer bonding technique and that it will work in mass production.

To be successful, YMTC had to overcome several challenges, as illustrated below. YMTC Xtacking challenges Photo by Tom Coughlin YMTC said that their 3 rd generation Xtacking provides a 1Tb die with 6 planes that allows asynchronous multi-plane independent operations per plane. The company said that Xtacking opened possibilities for many applications as shown below.

YMTC future plans Photo by Tom Coughlin FADU pointed out that power and heat will be the greatest challenges for SSDs used in data center applications and they indicate that this is a major focus of their product development. Power is also an issue for many embedded devices. During Samsung’s keynote they showed a 45% power efficiency (MB/s per mA) with their UFS 4.

0 product compared to prior generation UFS 3. 1, using their own controller and 7 th generation VNAND. The product will be available in Q# 2022.

Samsung was also showing their 2 nd generation SmartSSD with PCIe support for near data processing. The product includes an AMD versal adaptive SoC and ARM plus HW accelerator IP. The product boosts a 6X data rate improovement running a PostgreSQL scan compared to a regular PCIe 4.

0 SSD. Solidigm, now part of SK hynix, was Intel’s NAND and SSD business. At the 2022 FMS the company announced its first Solidigm branded product, the P41 Plus SSD.

This SSD is a PCIe 4. 0 NVMe product for the client PC market. The drive features 144-layer 3D NAND and offers up to 4.

1 GB/s sequential read speed. Capacities go from 512GB to 2TB. Solidigm is offering software running on the host machine called Solidigm Synergy that includes a storage driver and a Windows application with health monitoring tools.

The P41 Plus includes SLC as well as TLC flash and Synergy software to provide host-managed caching by monitoring usage patterns to keep the most frequently accessed data in the cache. A demonstration showed the P41 Plus running twice as fast (reading data) using the Synergy software than running without the software. In a briefing Solidigm said that the P41 Plus can turn some of the SLC flash into TLC flash and back again as needed.

The Synergy software leverages caching developments originally created for Intel’s Optane memory. The figure below was from the SK hynix keynote talk. Solidigm’s Synergy software Photo from Ron Dennison Solidigm was also comparing their D7-P5520 versus an un-named competitor enterprise SSD showing significant performance improvements.

The core technologies of Solidigm’s 4D NAND are a sideway source to reduce alignment dependency, peripheral logic under cells and and advanced charge tracp cell that has a wider cell voltage distribution window (~6V was shown on a slide). During the keynote they also dropped an announcement of a 238-layer 512Gb TLC die (6 more layers than Micron’s recently announced 232-layer 3D NAND. Mass production of this chip is to start in the first half of 2023, see below.

There has been a 10% performance gain with each 4D NAND generation. Solidigm’s 238-layer NAND die Photo by Ron Dennison Solidigm/SK hynix also announced a 175-layer 1Tb QLC NAND that will start mass production in Q4’22 and said that a QLC for mobile products with the 238-layer technology is in development. The company also indicated that it is working on a PLC (5-bits per cell) NAND device for nearline applications.

This technology is targeted at a 192-layer 1. 67Tb die. During an FMS session on Thursday, SK hynix demonstrated a next-generation intelligent storage product and a Key Value Store Computational storage device (KV-CSD) with improved write and read capabilities for high performance computing Samsung also was showing their first PCIe 5.

0 SSD that they said was in mass production, the PM1742, shown below (it won an award at the 2022 CES). As shown, moving to PCIe Gen 4 from 3 significantly improved bandwidth and power efficiency. Samsung Enterprise PCIe Gen5 SSD Photo by Tom Coughlin Samsung also announced a 24G dual port SAS SSD (the PM1653) which shows a 2X bandwidth and 31% power efficiency increase compared to earlier 12G SAS SSDs.

Samsung said that its V8 TLC VNAND product will be released with physical scaling and improved storage capacity with the same volume. Samsung also talked about die-stacking technology for their SSDs for very high-capacity implementations. The chart below gives their projections of 32-die stacking capacities, with 1PB capacities possible in 10 years.

Samsung was also showing their broad range of SSD form factors for different applications and enclosures. Samsung vision of 32-die stack 1PB in 10 years Photo by Tom Coughlin NVIDIA spoke during the Samsung keynote talking about GPU direct storage, showing and AIC JBOF with a Samsung SSD and a BlueField DPU, see below. They also discussed PBSSD, an NVMe subsystem for disaggregated storage with greater rack efficiency for PB-scale storage.

NVIDIA PBSSD petabyte scale disaggregated storage Photo by Tom Coughlin Neo Semiconductor in their keynote spoke about their new NAND Flash and DRAM architectures. With their aggregated sense amplifier, higher plane architecture, their X-NAND provides 3X higher random read/write speed and 20X higher sequential R/W speed. Their X-DRAM has 50% lower activation latency and requires only 15% of refresh power consumption.

The figure below shows the basic concept applied to DRAM. Neo Semi’s X-DRAM concept Photo by Tom Coughlin By aggregating four bit-lines to a sense amplifier they can create 4 planes of DRAM memory and shorter bit lines with shorter bit line delay and lower power consumption. This also results in much higher data throughput.

This can be applied with even more aggregation of the sense amplifiers to increase performance even further. The figure below shows the overall modelled advantages of this architectural change for DRAM. Neo Semiconductor X-DRAM modeled advantages Photo by Tom Coughlin A similar approach can be taken with NAND flash by aggregating page buffers.

The figure below shows a first generation TLC X-NAND with the four page buffers instead of one and a second generation with eight page buffers. Note that the first generation is modelled to have 1. 6GB/s data rates versus 160MB/s with conventional NAND.

Neo speculates that X-NAND could provide a storage class memory layer between SSDs and DRAM using SLC or MLC NAND and an SSD storage layer using TLC and QLC NAND. They even discussed the possibility of replacing HDDs with PLC or HLC (six bits per cell) NAND. Neo Semi’s X-NAND modeled advantages Photo by Tom Coughlin The 2022 FMS included several new flash memory announcements.

Solidigm (SK hynix) announced a 238-layer NAND flash as well as a PLC NAND flash die. WDC/Kioxia talked about 500+ layers by 2032. YMTC talked about their 3 rd generation wafer bonding technology, Samsung was showing their PCIe Gen 5 SSD and said 32 die stacks with 1PB capacity would be possible in 10 years.

FADU talked about the need to control power and temperature in enterprise SSDs. NVIDIA discussed PBSSD for petabyte scale NVMe disaggregated storage. Neo Semiconductor talked about a higher performance NAND and DRAM architecture.

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