Intel’s Push For UCIe Will Enable Lower System Costs

Enterprise Tech Intel’s Push For UCIe Will Enable Lower System Costs Tom Coughlin Contributor Opinions expressed by Forbes Contributors are their own. Following New! Follow this author to stay notified about their latest stories. Got it! Oct 13, 2022, 10:44pm EDT | New! Click on the conversation bubble to join the conversation Got it! Share to Facebook Share to Twitter Share to Linkedin Silicon Die getty At the Intel Innovation Forum in late September, CEO Pat Gelsinger spoke about building a new type of foundry, making systems, rather than chips.

A key part of this idea is to use smaller focused technology chips called chiplets made by multiple companies, intimately connected with each other as shown below. Intel said that they would like to provide foundry services not just for the chiplets, but also for the packaging of entire chiplet-based systems. Pat Gelsinger, Intel CEO, talks about chiplets and UCIe Photo from Intel Innovation Forum To facilitate connecting these chiplets together an open standards body defining the way that these chips connect together was created, the Universal Chiplet Interconnect Express (UCIe), or as Gelsinger said, a UCI ecosystem.

Over 80 companies have joined this effort to define a die-to-die interconnect and serial bus between chiplets. Chiplet technology allows using different production technologies for different functions. This is important where the smallest lithography chip production has become ever more expensive.

This has important implications for memory technology, where, for instance much of the real estate on a processor chip today is used for SRAM cache memory. At the 2022 SNIA Storage Developers Conference Jim Handy and I looked at how the use of memory could change with the move to chiplet-based system architectures. Let’s take a look at this argument.

The SRAM made on a processor chip is big and very expensive. This makes the use of a chiplet to remove some of this SRAM memory from the processor chip very attractive. Let’s go through an example of why this is so.

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5MB for L3. This adds up to 2. 6MB of SRAM cache.

Thus, the SRAM cost would be about $100/2. 6MB = $38/MB. On the other hand, a 4 megabit standalone SRAM chip (½MB) retails for $6 and thus costs $12/MB.

So, using a memory chiplet will reduce the processor cache costs. This economics will help drive the move to chiplet technologies, based upon memory alone. But SRAM is orders of magnitude more costly than DRAM (DRAM is currently $3/GB, or $0.

003/MB – Three hundredths of a cent!) and NAND flash and will soon be more expensive than a non-volatile memory, like MRAM. Chiplet technology allows combining chiplets with many different memory technologies into a package. Costs go down using chiplets and it opens the door to interesting combinations of technologies.

Today’s chiplets are planar or 2. 5D structures (limited chip stacking), but future packaging products will evolve to include the use of true 3D chip stacking with advanced interconnects. These moves to heterogeneous packaging promise to create dense collections of advanced technologies that could combine the best options for various functions at much lower cost than putting all these technologies into a single chip.

Intel committed itself to building system foundries using advanced packaging such as the UCIe standard for connecting chiplets. Using chiplets with a fast and universal interconnect offers lower cost products and paves the way for even more advanced heterogenous integration technologies. Follow me on Twitter or LinkedIn .

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